 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| HM62G18512 Series 8M Synchronous Fast Static RAM (512k-word x 18-bit) ADE-203-1185 (Z) Preliminary Rev. 0.0 Jun. 12, 2000 Description The HM62G18512 is a synchronous fast static RAM organized as 512-kword x 18-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119bump BGA. Note: All power supply and ground pins must be connected for proper operation of the device. Features * * * * * * * * * * * * * Power supply: 3.3 V +10%, -5% Clock frequency: 200 MHz to 250 MHz Internal self-timed late write Byte write control (2 byte write selects, one for each 9-bit) Optional x36 configuration HSTL compatible I/O Programmable impedance output drivers User selective input trip-point Differential, HSTL clock inputs Asynchronous G output control Asynchronous sleep mode Limited set of boundary scan JTAG IEEE 1149.1 compatible Protocol: Single clock register-register mode Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications. HM62G18512 Series Ordering Information Type No. HM62G18512BP-4 HM62G18512BP-5 Access time 2.1 ns 2.5 ns Cycle time 4.0 ns 5.0 ns Package 119-bump 1. 27 mm 14 mm x 22 mm BGA (BP-119A) Pin Arrangement 119-bumps BGA 1 A 2 3 4 NC NC 5 6 7 VDDQ SA0 SA6 SA4 SA2 VDDQ SA8 SA18 NC NC B NC NC SA7 C NC SA13 SA3 VDD SA5 SA1 D DQb0 NC VSS ZQ SS G VSS DQa4 NC VSS NC DQa5 E NC DQb1 VSS F VDDQ NC VSS VSS DQa6 VDDQ VSS NC DQa7 G H NC DQb2 SWEb NC DQb3 NC VSS NC VSS DQa8 NC J VDDQ VDD VREF VDD VREF VDD VDDQ K NC DQb8 VSS K K VSS NC DQa3 L DQb7 NC VSS SWEa DQa2 NC NC VDDQ M N VDDQ DQb6 VSS SWE VSS DQb5 NC VSS SA16 VSS DQa1 NC NC DQa0 P NC DQb4 VSS SA14 VSS R NC SA9 M1 VDD M2 SA10 NC T NC SA17 SA11 NC SA12 SA15 ZZ U VDDQ TMS TDI TCK TDO NC VDDQ (Top view) 2 HM62G18512 Series Pin Description Name VDD VSS VDDQ VREF K K SS SWE SAn SWEx G ZZ ZQ DQxn M1, M2 TMS TCK TDI TDO NC I/O type Supply Supply Supply Supply Input Input Input Input Input Input Input Input Input I/O Input Input Input Input Output -- Descriptions Core power supply Ground Output power supply Input reference: provides input reference voltage Clock input. Active high. Clock input. Active low. Synchronous chip select Synchronous write enable Synchronous address input Synchronous byte write enables Asynchronous output enable Power down mode select Output impedance control Synchronous data input/output Output protocol mode select Boundary scan test mode select Boundary scan test clock Boundary scan test data input Boundary scan test data output No connection 1 x = a, b n = 0, 1, 2...8 n = 0, 1, 2...18 x = a, b Notes M1 VSS M2 VDD Protocol Synchronous register to register operation Notes 2 Notes: 1. ZQ is to be connected to V SS via a resistance RQ where 150 RQ 300 , if ZQ = VDDQ or open, output buffer impedance will be maximum. A case of minimum impedance, it needs to connect over 120 between ZQ and V SS . 2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either VDD or VSS respectively. The state of the Mode control inputs must be set before power-up and must not change during device operation. Mode control inputs are not standard inputs and may not meet VIH or VIL specification. This SRAM is tested only in the synchronous register to register operation. 3 HM62G18512 Series Block Diagram 19 A0 to A18 JTAG register R-Add register 19 W-Add register MUX Row decoder 19 Memory cell array (512k x 18) Column decoder 1 SS JTAG register SWE JTAG register 2 SWEx JTAG register G SS register WRC WA SWE register Match SWEx register 2 SA Multiplex DOC JTAG register CLK control JTAG register JTAG register D-in register D-out register K K OB 18 DQa0-8 DQb0-8 ZZ VREF JTAG register ZQ JTAG register TDI TCK TMS Impedance contorol logic JTAG tap controller TDO 4 HM62G18512 Series Operation Table ZZ H L L L L L L SS x H x L L L L G x x H L x x x SWE x x x H L L L SWEa SWEb K x x x x L L H x x x x L H L x L-H x L-H L-H L-H L-H K x H-L x H-L H-L H-L H-L Operation sleep mode Dead (not selected) Dead (Dummy read) Read Write a, b byte Write a byte Write b byte DQ (n) High-Z x High-Z x High-Z High-Z High-Z DQ (n + 1) High-Z High-Z High-Z Dout (a,b)0-8 Din (a,b)0-8 Din (a)0-8 Din (b)0-8 Notes: 1. x means don't care for synchronous inputs, and H or L for asynchronous inputs. 2. SWE, SS, SWEa to SWEb, SA are sampled at the rising edge of K clock. 3. Although differential clock operation is implied, this SRAM will operate properly with one clock phase (either K or K) tied to V REF. Under such single-ended clock operation, all parameters specified within this document will be met. 5 HM62G18512 Series Absolute Maximum Ratings Parameter Input voltage on any pin Core supply voltage Output supply voltage Operating temperature Storage temperature Junction temperature Output short-circuit current Latch up current Package junction to case thermal resistance Package junction to ball thermal resistance Symbol VIN VDD VDDQ TOPR TSTG Tj I OUT I LI JC JB Value -0.5 to VDDQ + 0.5 -0.5 to 3.9 -0.5 to 2.2 0 to 70 -55 to 125 110 25 200 2 5 Unit V V V C C C mA mA C/W C/W 5, 7 6, 7 Notes 1, 4 1 1, 4 Notes: 1. All voltage is referred to VSS . 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The supply voltage application sequence need to be powered up in the following manner: V SS , VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 3.9 V, whatever the instantaneous value of VDDQ. 5. JC is measured at the center of mold surface in fluorocarbon (See Figure "Definition of Measurement"). 6. JB is measured on the center ball pad after removing the ball in fluorocarbon (See Figure "Definition of Measurement"). 7. These thermal resistance values have error of 5C/W. JC T.C. JB Fluorocarbon T.C. Fluorocarbon Definition of Measurement 6 HM62G18512 Series Note: The following the DC and AC specifications shown in the Tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. DC Operating Conditions (Ta = 0 to 70C [Tj max = 110C]) Parameter Supply voltage (Core) Supply voltage (I/O) Supply voltage Input reference voltage (I/O) Input high voltage Input low voltage Clock differential voltage Clock common mode voltage Notes: 1. 2. 3. 4. Symbol VDD VDDQ VSS VREF VIH VIL VDIF VCM Min 3.135 1.4 0 0.65 Typ 3.30 1.5 0 0.75 Max 3.63 1.6 0 0.90 VDDQ + 0.3 VREF - 0.1 VDDQ + 0.3 0.90 Unit V V V V V V V V 1 4 4 2, 3 3 Notes VREF + 0.1 -- -0.5 0.1 0.55 -- -- -- Peak to peak AC component superimposed on V REF may not exceed 5% of VREF. Minimum differential input voltage required for differential input clock operation. See following figure. VREF = 0.75 V (typ). VDDQ VDIF VCM VSS Differential Voltage/Common Mode Voltage 7 HM62G18512 Series DC Characteristics (Ta = 0 to 70C, [Tj max = 110C], VDD = 3.3 V +10%, -5%) Parameter Input leakage current Symbol Min I LI -- -- -- -- Typ -- -- -- -- Max 2 5 100 700 Unit Notes A A mA mA 1 2 3 4 Output leakage current I LO Standby current I SBZZ VDD operating current, I DD4 excluding output drivers 4 ns cycle VDD operating current, I DD5 excluding output drivers 5 ns cycle Quiescent active power I DD2 supply current Output low voltage Output high voltage ZQ pin connect resistance Output low current Output high current VOL VOH RQ I OL I OH -- -- 600 mA 4 -- VSS VDDQ - 0.4 150 (VDDQ/2)/[(RQ/5)-15%] -- -- -- 250 -- 200 VSS + 0.4 VDDQ 300 (VDDQ/2)/[(RQ/5)+15%] mA V V mA 5 6 6 7, 9 8, 9 (VDDQ/2)/[(RQ/5-4)+15%] -- (VDDQ/2)/[(RQ/5-4)-15%] mA Notes: 1. 0 Vin V DDQ for all input pins (except VREF, ZQ, M1, M2 pin). 2. 0 Vout V DDQ, DQ in High-Z. 3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, Iout = 0 mA, Spec is guaranteed at 75C junction temperature. 4. Iout = 0 mA, read 50%/write 50%, VDD = VDD max, VIN = VIH or VIL, Frequency = minimum cycle. 5. Iout = 0 mA, read 50%/write 50%, VDD = VDD max, VIN = VIH or VIL, Frequency = 3 MHz. 6. Minimum impedance push pull output buffer mode, IOH = -6 mA, IOL = 6 mA. 7. Measured at V OL = 1/2 VDDQ. 8. Measured at V OH = 1/2 VDDQ. 9. Output buffer impedance can be programmed by terminating the ZQ pin to V SS through a precision resister (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 150 and 300 . If the status of ZQ pin is open, output impedance is maximum. Maximum impedance occurs with ZQ connected to VDDQ. The impedance update of the output driver occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of High-Z, therefore triggering an update. The user may choose to invoke asynchronous G updates by providing a G setup and hold about the K clock to guarantee the proper update. At power-up, the output impedance defaults to minimum impedance. It will take 2048 cycles for the impedance to be completely updated if the programmed impedance is much higher than minimum impedance. 8 HM62G18512 Series Capacitance (Ta = 25C, f = 1 MHz) Parameter Input capacitance (SAn, SS, SWE, SWEx) Input capacitance (K, K, G) Input/Output capacitance (DQxn) Note: Symbol CIN CCLK CIO Min -- -- -- Max 4 7 5 Unit pF pF pF Note 1 1 1 1. This parameter is sampled and not 100% tested. AC Characteristics (Ta = 0 to 70C, [Tj max = 110C], VDD = 3.3 V +10%, -5%) Test Conditions * * * * * * Input pulse levels (K, K): VDIF = 0.75 V, VCM = 0.75 V Input timing reference level (K, K): Differential cross point Input pulse levels (except K, K): VIL = 0.25 V, VIH = 1.25 V Input and output timing reference levels (except K, K): VREF = 0.75 V Input rise and fall time: 0.5 ns (10% to 90%) Measurement condition: the minimum impedance push pull output buffer mode, IOH = -6 mA, IOL = 6 mA * Output driver supply voltage: VDDQ = 1.5 V * Output load: See figure 16.7 16.7 DQ 16.7 50 5 pF 50 5 pF 50 0.75 V 50 0.75 V 0.75 V 9 HM62G18512 Series Single Differential Clock Register-Register Mode (M1 = VSS, M2 = VDD ) HM62G18512 -4 Parameter CK clock cycle time CK clock high width CK clock low width Address setup time Data setup time Address hold time Data hold time Clock high to output valid Clock high to output hold Clock high to output valid (SS control) Clock high to output High-Z Output enable low to output Low-Z Output enable low to output valid Output enable low to output High-Z Sleep mode recovery time Sleep mode enable time Notes: 1. 2. 3. 4. 5. 6. Symbol t KHKH t KHKL t KLKH t AVKH t DVKH t KHAX t KHDX t KHQV t KHQX t KHQX2 t KHQZ t GLQX t GLQV t GHQZ t ZZR t ZZE Min 4.0 1.5 1.5 0.5 0.5 0.75 0.75 -- 0.5 -- -- 0.5 -- -- 10.0 -- Max -- -- -- -- -- -- -- 2.1 -- 2.1 2.5 -- 2.5 2.5 -- 10.0 -5 Min 5.0 1.5 1.5 0.5 0.5 1.0 1.0 -- 0.5 -- -- 0.5 -- -- 10.0 -- Max -- -- -- -- -- -- -- 2.5 -- 2.5 3.0 -- 2.5 2.5 -- 10.0 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 2 2 2, 5 2, 3 2, 5 2, 3 2, 3 6 2, 3, 6 Notes Guaranteed by design. Refer to the Test Conditions. Transitions are measured at start point of output high impedance from output low impedance. Output driver impedance updates during High-Z. Transitions are measured 50 mV from steady state voltage. When ZZ is switching, clock input K must be at same logic levels for reliable operation. 10 HM62G18512 Series Timing Waveforms Read Cycle-1 tKHKH K K tAVKH SA A1 tAVKH SS tAVKH SWE tKHAX A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SWEx tKHQX DQ Do 0 tKHQV Note: G, ZZ = VIL Do 1 Do 2 11 HM62G18512 Series Read Cycle-2 (SS Controlled) tKHKH K K tAVKH SA A1 tAVKH SS tAVKH SWE tKHAX tKHAX A3 tKHAX A4 tKHKL tKLKH SWEx tKHQZ DQ Do 0 Do 1 tKHQX2 Note: G, ZZ = VIL Do 3 12 HM62G18512 Series Read Cycle-3 (G Controlled) tKHKH K K tAVKH SA A1 tAVKH SS tAVKH SWE tKHAX A2 tKHAX tKHAX A3 A4 tKHKL tKLKH SWEx G tGHQZ DQ Note: ZZ = VIL Do 0 Do 1 tGLQX tGLQV Do 3 13 HM62G18512 Series Write Cycle tKHKH K K tAVKH SA A1 tAVKH SS tAVKH SWE tAVKH SWEx G tDVKH DQ Di 0 Di 1 tKHDX Di 2 Di 3 tKHAX tKHAX A2 tKHAX tKHAX A3 A4 tKHKL tKLKH Note: ZZ = VIL 14 HM62G18512 Series Read-Write Cycle READ tKHKH K K tAVKH SA SS tAVKH SWE tAVKH SWEx G tGHQZ tDVKH DQ Do 0 tKHQX tKHQV Do 1 Di 3 tGLQX tKHDX tGLQV Do 4 tKHQZ Di 6 tKHAX tKHAX A1 tAVKH tKHAX A3 A4 tKHAX A6 A7 READ (G control) tKHKL tKLKH WRITE READ DEAD (SS control) WRITE Note: ZZ = VIL ZZ Control tKHKH K K tAVKH SA SS tAVKH SWE SWEx ZZ Sleep active DQ tZZR Do 1 tZZE Sleep off Sleep active tKHAX A1 tKHAX tKHKL tKLKH Note: G = VIL 15 HM62G18512 Series Boundary Scan Test Access Port Operations In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 1990. But does not implement all of the functions required for 1149.1 compliance The HM62Gxx series contains a TAP controller. Instruction register, Boundary scans register, Bypass register and ID register. Test Access Port Pins Symbol I/O TCK TMS TDI TDO Name Test clock Test mode select Test data in Test data out Note: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. To disable the TAP, TCK must be connected to V SS . TDO should be left unconnected. To test Boundary scan, ZZ pin need to be kept below V REF - 0.4 V. TAP DC Operating Conditions (Ta = 0 to 70C, [Tj max = 110C]) Parameter Boundary scan input high voltage Boundary scan input low voltage Boundary scan input leakage current Boundary scan output low voltage Boundary scan output high voltage Notes: 1. 0 Vin V DD for all logic input pin. 2. I OL = 8 mA. 3. I OH = -8 mA. Symbol VIH VIL I LI VOL VOH Min 2.0 -0.5 -2 -- 2.4 Max VDD + 0.3 0.8 2 0.4 -- Unit V V A V V 1 2 3 Notes 16 HM62G18512 Series TAP AC Characteristics (Ta = 0 to 70C, [Tj max = 110C]) Parameter Test clock cycle time Test clock high pulse width Test clock low pulse width Test mode select setup Test mode select hold Capture setup Capture hold TDI valid to TCK high TCK high to TDI don't care TCK low to TDO unknown TCK low to TDO valid Note: Symbol t THTH t THTL t TLTH t MVTH t THMX t CS t CH t DVTH t THDX t TLQX t TLQV Min 67 30 30 10 10 10 10 10 10 0 -- Max -- -- -- -- -- -- -- -- -- -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Note 1. t CS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. TAP Test Conditions * * * * Input pulse levels: 0 to 3.0 V Input and output timing reference levels: 1.5 V Input rise and fall time: 2 ns (10% to 90%) (typ) Output Load: See figure VT = 1.5 V DUT Z0 = 50 TDO 50 17 HM62G18512 Series TAP Controller Timing Diagram tTHTH TCK tTHTL tTLTH tMVTH TMS tTHMX tDVTH TDI tTHDX tTLQV tTLQX TDO RAM Address tCS tCH Test Access Port Registers Register name Instruction register Bypass register ID register Boundary scan register Length 3 bits 1 bit 32 bits 51 bits Symbol IR [0;2] BP ID [0;31] BS [1;51] Note 18 HM62G18512 Series TAP Controller Instruction Set IR2 0 0 0 0 1 1 1 1 IR1 0 0 1 1 0 0 1 1 IR0 0 1 0 1 0 1 0 1 Instruction SAMPLE-Z IDCODE SAMPLE-Z BYPASS SAMPLE BYPASS BYPASS BYPASS Tristate all data drivers and capture the pad value Operation Tristate all data drivers and capture the pad value Note: This Device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1. 19 HM62G18512 Series Boundary Scan Order Bit No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Bump ID 5R 6T 4P 6R 5T 7T 7P 6N 6L 7K 5L 4L 4K 4F 6H 7G 6F 7E 6D 6A 6C 5C 5A 6B 5B 3B Signal name M2 SA15 SA14 SA10 SA12 ZZ DQa0 DQa1 DQa2 DQa3 SWEa K K G DQa8 DQa7 DQa6 DQa5 DQa4 SA2 SA1 SA5 SA4 SA18 SA8 SA7 Bit No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Bump ID 2B 3A 3C 2C 2A 1D 2E 2G 1H 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R Signal name NC SA6 SA3 SA13 SA0 DQb0 DQb1 DQb2 DQb3 SWEb ZQ SS NC NC SWE DQb8 DQb7 DQb6 DQb5 DQb4 SA11 SA9 SA16 SA17 M1 Notes: 1. Bit number1 is the first scan bit to exit the chip. 2. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a "Place Holder". Placeholder registers are internally connected to V SS . 3. In Boundary scan mode, differential input K and K are referred to each other and must be at opposite logic levels for reliable operation. 4. ZZ must remain at VIL during boundary scan. 5. In boundary scan mode, ZQ must be driven to V DDQ or VSS supply rail to ensure consistent results. 6. M1 and M2 must be driven to VDD or VSS supply rail to ensure consistent results. 20 HM62G18512 Series ID register Bit No. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value x x x x 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Vendor Revision No. Depth Width Use in the future Vendor ID No. Fix TAP Controller State Diagram Test-LogicReset 0 Run-Test/ Idle 1 SelectDR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 SelectIR-Scan 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1 1 0 Note: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK. 21 HM62G18512 Series Package Dimensions HM62G18512BP Series (BP-119A) Unit: mm 4x 0.20 0.35 C 4 x C1.2 14.00 Y C 7654321 A B C D E F G H J K L M N P R T U 1.27 A Pin 1 Index 21.0 0.10 22.00 B 13.0 0.10 0.60 0.10 119 x 0.75 0.15 0.30 M C A B 0.15 M C Details of the part Y Hitachi Code JEDEC EIAJ Mass (reference value) BP-119A Conforms -- 1.2 g 22 2.10 0.25 1.27 0.15 C HM62G18512 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Hitachi, Ltd. Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 URL NorthAmerica Europe Asia Japan : : : : http://semiconductor.hitachi.com/ http://www.hitachi-eu.com/hel/ecg http://www.hitachi.com.sg/grp3/sicd http://www.hitachi.co.jp/Sicd/indx.htm Hitachi Asia Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3rd Flr, Hung Kuo Building, No.167, Tun Hwa North Road, Taipei (105) Taiwan Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Telex: 23222 HAS-TP Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7th Flr, North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe GmbH Electronic Components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 585160 Copyright (c) Hitachi, Ltd., 2000. All rights reserved. Printed in Japan. Colophon 1.0 23 |
Price & Availability of HM62G18512BP-4
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |